Seal ring structure for radio frequency integrated circuits

ABSTRACT

Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.

This is a division of U.S. patent application Ser. No. 09/933,965,filing date Aug. 22, 2001 now U.S. Pat. No. 6,537,849, Seal RingStructure For Radio Frequency Integrated Circuits, assigned to the sameassignee as the present invention.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention generally relates to an encapsulation process used insemiconductor manufacturing and, more particularly, to a method ofencapsulation that improves isolation of radio frequency (RF) signals inthe fabrication of integrated circuits.

(2) Description of Prior Art

As integrated circuit (IC) speeds increase, seal rings have beenincorporated into the device encapsulation in order to reduce radiofrequency (RF) interference and signal cross coupling. The seal ring isgrounded or connected to a signal ground such as a DC supply line toeliminate the effect of interference. The seal ring may be part of thedevice packaging scheme; in this case a conductive lid is typicallyconnected to the seal ring. Specific to this invention, the seal ringmay be incorporated into the IC substrate fabrication and may include aconductive covering over the substrate.

FIG. 1 shows in exploded view a method where the seal ring isincorporated into the device package. A substrate 10 made of ceramicmaterial, for example, has an integrated circuit die 12 attached by aconductive epoxy or eutectic bond. The die 12 is electrically connectedto the substrate 10 using bond wires (not shown). A conductive seal ring14 is attached and grounded by internal connections (not shown). Thepackage is scaled using a lid 16 to prevent penetration by contaminantsand moisture.

FIG. 2 shows a top view of an IC die 20 where a seal ring 22 isincorporated. A plurality of bonding pads 24 are shown which may beeither signal inputs or outputs, or DC supply and ground. A portion ofthe circuit containing RF circuits 26 is shown. One problem with thismethod is that signals from the bonding pads 24 may be capacitivelycoupled to the seal ring 22. This may result in unwanted signalinterference appearing at one of the signal input or output bonding pads24. In addition, interference may be coupled to the RF circuit 26resulting in signal distortion.

Other approaches employing seal rings exist. U.S. Pat. No. 5,717,245 toPedder teaches a system using a dielectric multi-layer substrate whereRF interference is reduced by grounding certain areas and encapsulatingthe substrate within a conductive seal ring. U.S. Pat. No. 6,028,497 toAllen et al. teaches a system where RF signals are passed through anetwork of holes in the base plate of the module. The holes each consistof a conductive pin surrounded by, but electrically isolated from, aconductive cylindrical shroud, thereby forming a coaxial connection. Acompartmentalized seal ring attached to the top of the module segregatesdifferent circuit areas of the module. U.S. Pat. Nos. 5,864,092 and6,105,226 to Gore et al. teach methods employing a leadless chip carrierpackage where a grounded conductor protrudes between input and outputsignal pads thereby preventing interference. U.S. Pat. No. 5,998,245 toYu teaches a method where ESD protection is incorporated into a sealring structure on an IC die. U.S. Pat. No. 6,028,347 to Sauber et al.teaches a method where a portion of the seal ring is formed in trenchesin the semiconductor surface. An encapsulating plastic covering over thesurface fills the trenches thereby preventing movement of the cover andreducing stresses due to thermal expansion.

SUMMARY OF THE INVENTION

A principal object of the present invention is to provide a method thatreduces cross coupling between circuits and pads in an integratedcircuit.

Another object of the present invention is to provide a method thatprevents cross coupling between circuits caused by the seal ring in anintegrated circuit.

These objects are achieved by using a method where a seal ring is formedby stacking interconnected metal layers along the perimeter of theintegrated circuit (IC). Discontinuities are formed in the seal ringencapsulating different sections of the IC. There are no overlapsbetween discontinuities in the seal ring thus isolating signals utilizedon different sub-circuits within the IC. To further reduce unwantedsignal coupling, the distances between the seal ring and both signalpads and circuits are enlarged. Electrical connection is made betweenthe deep N-well and the seal ring to encapsulate the substrate andminimized signal coupling to the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of thisdescription, there is shown:

FIG. 1 schematically illustrating an exploded view cross-sectionalrepresentation of a prior art example employing seal rings;

FIG. 2 schematically illustrating a top view cross-sectionalrepresentation of a prior art example employing seal rings;

FIG. 3 schematically illustrating in cross-sectional representation apreferred embodiment of the present invention;

FIG. 4 schematically illustrating a top view of a preferred embodimentof the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention uses a method where a seal ring is formed bystacking interconnected conducting layers along the perimeter of theintegrated circuit (IC). The embodiment provided herein describes amethod of creating the seal ring and connecting the seal ring to thedeep N-well.

Refer to FIG. 3, depicting in cross-section a portion of an integratedcircuit die where the seal ring is formed. A substrate 30 is provided.The substrate layer 30 may contain underlying layers, devices,junctions, and other features (not shown) formed during prior processsteps. The cut line 31 represents the outer edge of the IC die ofinterest. During subsequent processing, the die would be separated froman adjacent IC die (not shown) on the substrate 30 along that cut line31. A deep N-well region 32 is formed as is conventional in the art. Ap+source/drain (S/D) region 34 formed by conventional techniques isisolated from the remainder of the underlying circuitry (not shown) byshallow trench isolation 36. A silicide 38 is formed over the S/D region34 providing a low resistance connection to the S/D region 34. Contacts40 through first interlevel dielectric layer 42 make electricalconnection to the first conductive layer 44. A plurality of via layers46a-46e through dielectric layers 48a-48e, respectively, make electricalcontact to a plurality of conductive layers 44 and 50a-50d,respectively. A top conductive layer 52 is then provided. This isfollowed by a passivation layer 54 composed of USG oxide, for example,deposited by chemical vapor deposition (CVD), for example, to athickness of between about 8000 Å and 20,000 Å. This completes the sealring 62 composed of the conductive layers 44, 50a-50d and 52 and vialayers 46a-46e. The seal ring 62 makes electrical contact to the deepN-well 32 via contact 40, silicide 38 and S/D region 34. Typical widthsof the seal ring 62 are between about 5 μm to 15 μm.

A nitride layer 56 composed of Si₃N₄ is then conformally deposited byCVD to a thickness of between about 2000 Å and 10,000 Å. The CVD processprovides excellent step coverage along the sidewalk of the structure. Apolyimide layer 58 is then deposited by spin-on techniques to athickness of between about 2 μm and 6 μm.

When the completed IC is electrically connected in a circuit, the deepN-well 32 is electrically connected to a positive supply voltage (Vdd)thereby holding the deep N-well 32 and seal ring 62 at signal ground.This minimizes signal coupling within the substrate and the S/D region.

Referring now to FIG. 4 showing a top view of a portion of an integratedcircuit 60, a portion of seal ring 62 and an important point of thepresent invention is depicted. Notice that there are discontinuities inthe seal ring 62. For example, the spacing between adjacent sections ofthe seal ring 62 is between about 10 and 30 microns. More specifically,the seal ring 62 is spaced further from signal pad 64 and radiofrequency circuit 66 than from signal ground pad 68. Typical distancesbetween the seal ring and signal ground pads would be between about 10μm and 30 μm, while distances between the seal ring and signal pinswould be between about 20 μm and 50 μm. It should be noted that both DCground pins and fixed DC voltage supply pins are effectively signalgrounds. The additional spacing between the seal ring 62 and signal pads64 and radio frequency circuits 66 reduces the coupling between distinctcircuits. The breaks in the seal ring 62 prevent interference from beingpropagated to other sub-circuits within the integrated circuit. Itshould also be noted that preferably, the seal ring 62 breaks do notoverlap along the perimeter of the integrated circuit 60; this furtherreduces the potential for signal interference. If the seal ring 60breaks must overlap (not preferred), then the distance between thedifferent portions of the seal ring must be increased.

The present invention is achieved by using a method where a seal ring isformed by stacking interconnected conductive layers along the perimeterof the IC. Discontinuities formed in the seal ring encapsulatingdifferent sections of the IC isolate signals utilized on differentsub-circuits within the IC. To further reduce unwanted signal coupling,the distances between the seal ring and both signal pads and circuitsare enlarged. Electrical connection made between the deep N-well and theseal ring encapsulates the substrate and minimizes signal coupling tothe substrate.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A seal ring for an integrated circuit wherein said seal ringsurrounds an active region of the integrated circuit and comprisesalternate first and second sections, the first sections arediscontinuous and spaced from the active region to form an innerperimeter for surrounding said active region, and the second sectionsare discontinuous and spaced from the active region to form an outerperimeter for surrounding said active region, said outer perimetersurrounding said inner perimeter.
 2. The seal ring according to claim 1wherein said integrated circuit further comprises signal pads, groundpads and radio frequency circuits.
 3. The seal ring according to claim 2wherein a spacing between said seal ring and said signal pads or saidradio frequency circuits is greater than a spacing between said sealring and ground pads.
 4. The seal ring according to claim 3 wherein thespacing between said seal ring and said signal pads or said radiofrequency circuits is between about 20 and 50 microns.
 5. The seal ringaccording to claim 3 wherein the spacing between said seal ring and saidground pads is between about 10 and 30 microns.
 6. The seal ringaccording to claim 1 wherein a spacing between said first and secondsections is between about 10 and 30 microns.
 7. The seal ring accordingto claim 1 wherein a width of said seal ring is between about 5 and 15microns.
 8. The seal ring according to claim 1 wherein said active areais a semiconductor device comprising at least one N-well.
 9. The sealring according to claim 8 wherein said seal ring is electricallyconnected to said N-well via a contact, a silicide and a source/drainregion of said integrated circuit.
 10. The seal ring according to claim8 wherein said N-well is electrically connected to a positive supplyvoltage (Vdd).
 11. The seal ring according to claim 1 wherein the firstsections do not overlap the second sections.
 12. A semiconductor devicewith a seal ring for an integrated circuit, comprising: alternate firstand second sections of the seal ring, discontinuous and spaced apartfrom an active region of the integrated circuit; wherein the first andsecond sections forms a separate inner perimeter and an outer perimeterfor surrounding the active region.
 13. The semiconductor deviceaccording to claim 12 wherein said integrated circuit further comprisesfirst pads, second pads and circuits.
 14. The semiconductor deviceaccording to claim 13 wherein a spacing between said seal ring and saidfirst pads or said circuits is greater than a spacing between said sealring and said second pads.
 15. The semiconductor device according toclaim 12 wherein said first pads, second pads and circuits respectivelycomprises signal pads, ground pads and radio frequency circuits.
 16. Thesemiconductor device according to claim 15 wherein the spacing betweensaid seal ring and said signal pads or said radio frequency circuits isbetween about 20 and 50 microns.
 17. The semiconductor device accordingto claim 16 wherein the spacing between said seal ring and said groundpads is between about 10 and 30 microns.
 18. The semiconductor deviceaccording to claim 12 wherein said active area is a semiconductor devicecomprising at least one N-well, and said seal ring is electricallyconnected to said N-well via a contact, a silicide and a source/drainregion of said integrated circuit.
 19. The semiconductor deviceaccording to claim 12 wherein the first sections do not overlap thesecond sections.